Real-time end of packet signal generator

ABSTRACT

Provided is a circuit for signalling the real-time end of a local area network packet as the packet is being pulled off a transmission medium and stored in memory. Storage of the packet is performed by a local area network coprocessor. The circuit monitors for the simultaneous occurrence of three conditions: the coprocessor is in a write-to-memory cycle; it is writing to the address of a status word pertaining to a packet; and the most significant bit of the status word is being set. If all three conditions are true, the circuit asserts the real-time end-of-packet signal.

BACKGROUND

A Local Area Network (LAN) is a communication network that providesinterconnection of a variety of data communicating devices within asmall area. Local Networks, p.2, by William Stallings, (MacMillanPublishing Company, 1984). A typical LAN is a computer network limitedto a geographically small area such as a plant site or an officebuilding. Various devices, such as computers, terminals, etc., are"plugged into" the network at various locations on the network. Eachsuch device is assigned an address so that digital communicationsbetween devices in the network may be properly delivered and received.

A well known and commercially accepted LAN standard is encompassed bythe Institute of Electrical and Electronic Engineers (IEEE) standard802.3. This standard is well known in industry under the name"Ethernet." The IEEE 802.3 standard features a Carrier Sense MultipleAccess with Collision Detection (CSMA/CD) media access method wherebytwo or more stations (devices) share a common bus transmission medium,typically a coaxial cable. To transmit over the LAN, a station or devicewaits for a quiet period on the bus, that is, no other station istransmitting, and then sends its intended message in bit serial form, atrates up to 10 Mbits/sec.

In the Ethernet/IEEE 802.3 system, messages between devices on thenetwork travel in packets, also known as frames, on the bus. An Ethernetpacket is displayed in FIG. 1. In examining the packet from head totail, we see that it consists of a 64-bit preamble, a 48-bit destinationaddress, a 48-bit source address, a 16-bit type field, and a data fieldthat may be from 46 bytes up to 1500 bytes long, wherein the last 4bytes constitute a 32-bit cyclic redundancy check (CRC) or frame checksequence. This Ethernet message format establishes the standard requiredfor widespread implementation of LAN technology.

All devices on LANs, such as computers, terminals, test equipment, etc.,must naturally possess LAN interface circuitry. A commonly used andimportant component of such circuitry is the Intel 82586 LANco-processor. The 82586 performs numerous functions including, amongmany other things, framing, preamble generation and stripping, sourceaddress generation, destination address checking and CRCgeneration/checking. Microsystem Component Handbook, Volume II, p. 7-288(Intel, 1984)

An important segment of LAN technology in which the 82586 plays acritical role involves data communications test equipment, commonlyknown as protocol analyzers. These devices are designed to monitor, aswell as generate, traffic on the LAN, such as an Ethernet transmissionbus, and then analyze it for the purposes of field service; electronicdata processing center support; network component research, development,manufacture, installation and service; and general network troubleshooting.

Such an analyzer may be required to "eavesdrop" on the LAN, examiningpacket traffic for packets of particular configurations. Used in such amanner, the analyzer reads packets off the LAN, without disrupting theirtransmission, and sends what it reads through a comparison process. Theprocess involves simultaneously placing the packets in memory andcirculating them past so-called trap machines which compare them withtarget configurations. The comparison process is known as filtering.Limited amounts of memory and other resources require that packets whichfail to match the target configurations be discarded while the matchingpackets are retained in memory.

Obviously, to make valid comparisons, a trap machine must be able todetermine the end of a packet so that it can distinguish one packet fromanother. Current solutions to this problem use the interrupt output pinof the 82586. In the rapid comparison cycles of some trap machines,however, the interrupt signal is inadequate in the case where twopackets arrive one immediately after the other, that is, "back-to-back,"because the interrupt signal arrives too late. In such a case, data fromthe second packet is already being stored before the interrupt from thefirst packet occurs. The solution requires generation of anotherreal-time signal which triggers before the data in the second packet isstored. The circuit to generate this real-time end-of-packet (EOP)signal is the present invention.

SUMMARY OF THE INVENTION

The preferred embodiment of present invention is intended for use withthe Intel 82586 Local Area Network (LAN) coprocessor. The 82586 pullsEthernet packets (frames) off a transmission medium and stores them, ina highly structured format, in host device memory. Each packet occupiesa single uniformly structured area of memory. Although packet size, andhence the size of the amount of memory it occupies may vary, thestructure of the memory area set out by the 82586 is essentially thesame for each packet. The 82586 keeps track of separate packets inmemory by setting the most significant bit of a status word itassociates with each packet's memory structure when each packet iscompletely received. The most significant bit of each status word isknown as the "complete" bit. The present invention provides for areal-time end-of-packet signal by monitoring for three concurrentconditions: the 82586 is in a write cycle; it is writing to the addressof a status word; and the complete bit is set. If all three of these aretrue, then the present invention asserts the end-of-packet signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an Ethernet packet.

FIG. 2 is a schematic block diagram of the shared memory where EthernetFrames are stored.

FIG. 3 is a block diagram of the format and structure of a typicalReceive Frame Descriptor.

FIG. 4 is a schematic block diagram of the preferred embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

To understand the preferred embodiment of the present invention, onemust first be familiar with operation of the Intel 82586 LANco-processor. The 82586 does much of the work in detecting the preamble,destination address, source address, type field and data field of anincoming Ethernet packet. It also initially stores away this informationfor each packet received. The 82586 performs these functions, amongothers, and communicates with its host device via shared memory. The82586 has direct access to the memory of the host device and mayautonomously transfer data blocks, thereby relieving the host CPU ofbyte transfer overhead. Microsystem Components Handbook, Volume II, p.7,287-321 (Intel, 1984).

Conceptually, the 82586 consists of two units, a command unit (CU) and areceive unit (RU). The CU executes commands stored in shared memory. TheRU performs all functions related to packet reception. The CU and RU mayperform their functions in parallel and host CPU intervention isnecessary only after the CU executes a string of commands or the RUstores a sequence of packets.

The shared memory structure critical to 82586 operation consists of fourparts: an initialization address; a system control block (SCB),containing, among other things, pointers to other parts of the sharedmemory; a command list (CL); and a receive frame area (RFA) for holdingan Ethernet packet. Most important, for the purposes of the presentinvention, is the RFA, which is essentially a memory structure, withinthe shared memory structure, pointed to by a receive frame pointer inthe SCB.

To receive frames, that is, Ethernet packets, the host CPU sets aside aproper amount of receive buffer space in memory and then enables the RUof the 82586. The RU then waits for frames (packets) and automaticallystores them in the RFA.

The RFA, consists of a receive descriptor list and a free buffer list.The receive descriptor list consists of individual receive framedescriptors (RFD), wherein each RFD pertains to a single received frame.The free buffer list consists of individual buffer descriptors (BD)which point to data buffers. Each RFD, is a chunk of memory used by the82586 to store the destination and source address, type field and statusof each frame received. Each RFD also contains pointers to the next RFDand to the free buffer list.

When a frame, as displayed in FIG. 1, arrives, the 82586 stores thedestination and source address and type field in the available RFD. Thedata field of the frame is then stuffed into data buffers, beginningwith the next free data buffer on free buffer list, which is pointed toby the current RFD. As one data buffer is filled, another isautomatically fetched until the entire data field of that frame isstored. Following receipt of an entire frame, various housekeepingtasks, such as fetching the address of the next free RFD, are performed.

In the preferred embodiment, each RFD in shared memory is configured asshown in FIG. 4. The status word at the head of the RFD includes a"complete bit," which is the most significant bit of the status word.The bits of the status word are set by the 82586. The complete bit isset when the frame peculiar to that RFD has been stored.

As noted in the Background, a real-time end-of-packet (EOP) signal,speedier than the generic interrupt asserted by the 82586, is requiredfor fast and reliable filtering. The present invention provides for suchan EOP signal by monitoring for the simultaneous occurrence of threeconditions: the 82586 is in a write-to-memory cycle; the write isaddressed to the status word of the RFD; and the complete-bit of thatstatus word is being set. If all three conditions are true, then areal-time EOP signal may be truthfully asserted. The preferredembodiment of the present invention uses a look-up read only memory(ROM) to determine if any given write is addressed to a status word. Ifa write is occurring, and it is addressed to one of the status words,and the complete-bit is a "1," then the EOP signal is asserted anddelivered to other devices for use.

FIG. 2 is a schematic block diagram of the shared memory structure whereEthernet Frames are stored by the 82586, known as the Receive Frame Area(RFA). As noted, the RFA consists of a list of Receive Frame Descriptors(RFD), wherein a single RFD is associated with a single receivedEthernet frame. In addition, each RFD, among other things, points to alist of Receive Buffer Descriptors (RBD), wherein each RBD, among otherthings, points to a buffer used for holding the data field of anEthernet frame. Also, whereas there is only one RFD per Ethernet frame,there may more than one RBD per RFD. That is, if the Ethernet frameholds too much data for a single RBD data buffer, then additional RBDsand data buffers will be linked until the frame is accommodated.

In FIG. 2, reference numeral 10 designates an RFA pointer which isresident at a pre-determined address in memory and which points to thefirst RFD in the RFA. Reference numeral 15 designates a status word,which is the first word of any RFD and indicates the status of thatparticular RFD. Reference numeral 20 designates a pointer to the nextRFD in the RFA. The next-RFD-pointer is one of the words following thestatus word in a RFD. Reference numeral 25 designates a pointer to thefirst RBD associated with the RFD in question. The first-RFD-pointer isthe word which follows the next-RFD-pointer in a RFD.

FIG. 3 is a block diagram displaying the format and structure of atypical RFD in detail. As can be seen from the diagram, each RFD, asused in the preferred embodiment of the present invention, consists of ablock of eleven contiguous 16-bit words. The first word, as noted above,is the status word pertaining to that RFD. The second word is a controlword. The third word points to the next RFD. The fourth word points tothe first RBD associated with that RFD. The fifth, sixth and seventhwords are used to hold the destination-address-field of the Ethernetframe to which that RFD pertains. The eighth, ninth and tenth word areused to hold the source-address-field of the frame. The eleventh wordholds the type-field of the frame. (The data-field of the frame isplaced in data buffers arranged by the RBDs associated with that RFD.)

Reference numeral 50 designates the most significant bit of the statusword of any RFD, known as the complete bit and also known as the C bit.The complete bit of a status word is set by the 82586 when the end ofthe Ethernet frame, associated with the particular RFD to which thatstatus word belongs, is completely stored in that RFD's RBD buffers. Thesetting of the complete bit is the key to the real-time end-of-packetsignal provided by the present invention.

As noted, the Receive Frame Area (RFA) of shared memory is where theEthernet frames are stored by the 82586, in the highly structured formatshown in FIG. 2. In the preferred embodiment of the present invention,the RFDs of the RFA are restricted to a certain range of contiguousaddresses within the RFA, wherein the range boundaries are known. Inaddition, given the format of RFDs, as shown in FIG. 3, every eleventhword in the RFD range will be a status word. The addresses of the statuswords are listed in a read only memory (ROM) chip.

When the 82586 has completed storing a frame, it sets the complete bitin the appropriate RFD status word, as noted above. In order to do so,the 82586 must have to write to the address of the status word inquestion. Hence, three conditions must be met to ensure that the end ofthe packet has been reached: the 82586is in a write cycle; it is writingto the address of a status word; and the complete bit is being set. Thepresent invention monitors these three events and goes "high" when allthree occur simultaneously, producing a real time end-of-packet signal.

To detect access by the 82586 to a status word, a look-upread-only-memory (ROM) is used, as noted, to determine if any write isaddressed to the status word of an RFD. Again, the RFDs are limited to acertain section of memory, in which every eleventh word is status word.The ROM may then eavesdrop on the host device memory address bus the82586 uses to write to memory. The ROM is designed to produce trueoutput when the status words are addressed.

In addition, the 82586 provides a write strobe pin which indicates thatthe 82586 is performing a write memory cycle. Microsystem ComponentsHandbook, volume II, p. 7-290 (Intel, 1984). This strobe signal may bemonitored to detect for a write cycle.

Finally, the setting of the complete bit may be determined by monitoringthe highest order data line, that is, the most significant bit, of thehost device memory data bus during write cycles.

FIG. 4 is a schematic block diagram of the preferred embodiment of thepresent invention, showing the principle thereof. Reference numeral 100of FIG. 4 designates the memory data bus over which the 82586 transmitsdata to the RFA. Reference numeral 110 of FIG. 4 designates the memoryaddress bus over which the 82586 selects the addresses in the RFA towhich it sends data over data bus 100. Reference numeral 115 designatesa means by which a ROM, designated by reference numeral 120,"eavesdrops" on the memory address bus. ROM 120 is loaded with "true"values at addresses corresponding to the addresses of status words inthe RFDs of the RFA. When status words are addressed in memory addressbus 110, the appropriate address-select lines of ROM 120 are alsoaddressed via means 115, thereby inducing a true output on the ROMoutput line, designated by reference numeral 130. All other addresssignals on memory address bus 110 will trigger a false output over ROMoutput line 130.

In addition, ROM output line 130 is combined with the most significantbit line of memory data bus 100 (via means 125) into an electronic ANDgate, designated by reference numeral 135. The most significant bit ofthe memory data bus, bit #15 in the preferred embodiment, will carrydata for the complete bit of the status words. Only when the output ofROM 120 and the complete bit are both true will the output of gate 135be true. Hence, two of the three qualifying conditions for assertion ofthe end-of-packet signal, that is, a status word is addressed and thecomplete bit is being set, must be true in order for gate 135 to outputa true value.

The output of gate 135 is delivered via means 142 to the input of aD-type flip-flop, designated by reference numeral 145. A D-typeflip-flop is designed to produce, as output, the signal which isdelivered to its input, when clocked. In the preferred embodiment,D-type flip-flop 145 is clocked via means 140 with write-strobe signalof the 82586. Hence, when the 82586 is in a write cycle, D-typeflip-flop 145 is clocked and will therefore produce, via output means150, the input signal delivered to it via means 142. Hence, means 150delivers an accurate real-time end-of-packet signal. It will be trueonly when all three conditions are met: the 82586 is in a write cycle, astatus word is being addressed and the complete bit is being set.

I claim:
 1. An apparatus for generating an end-of-packet signal, saidend-of-packet signal indicating, in real time, the occurrence, of thetail end of a local area network packet, said packet being transmittedon a local area network, said apparatus comprising:a local area networkcoprocessor, said coprocessor being resident in a host device, said hostdevice having memory and a memory address bus, said coprocessor beingadapted to receive local area network packets in bit serial form from alocal area network transmission medium, to store said packets in hostdevice memory in a uniform structured format, to create and maintain anassociated status word for each stored packet, the most significant bitof each said status word being set to true when the end of said packetis received, and to generate a write-strobe-signal whenever saidcoprocessor is in a write-to-memory cycle; a memory-address-comparisonmeans for comparing the address in host device memory to which saidcoprocessor is writing with addresses of said status words, and forgenerating an output signal when the address in host device memory beingwritten to by said coprocessor is the address of one of said statuswords; an electronic logic gate having as inputs said output signal ofsaid memory-address-comparison means and the most significant data-bitof data words written to said memory of said host device, saidelectronic logic gate producing a true output when both of said inputsare true; and a clocked flip-flop circuit, having as input the output ofsaid electronic logic gate, and having as clock signal thewrite-strobe-signal of said coprocessor, said clocked flip-flop circuitproducing as output said end-of-packet signal.
 2. An apparatus as inclaim 1 wherein the memory-address-comparison means comprises a look-upread only memory, said read only memory having address select lineswhich read on the memory address bus of said host device such thatwhatever address signals are placed on said address bus will drive saidaddress select lines, said read only memory being configured to producea true output when the address of one of said status words is placed onsaid address bus.